Gerald S. Williams         2282 Woodbarn Road, Macungie, PA 18062 (610)395-0160 gsw66@ptdprolog.net

QUALIFICATIONS

·       Over twenty years of professional software development experience, primarily with real-time embedded systems

·       Extensive and varied project management experience with both in-house and contract development

·       Experience with many communications systems and protocols including TCP/IP, SONET, and ATM

·       Insider experience with Lucent/Agere digital signal processors (helped design the DSP16000 instruction set)

·       Experience with Verilog coding, verification, and cosimulation

·       Designed reusable cosimulation frameworks using Verilog PLI interfaces

·       Extensive experience with lab testing (logic analyzers, protocol testers, etc.)

·       Experience with device validation, from requirements through lab testing

·       Extensive experience developing device models of all types, including statistical analysis and architectural feedback

·       Experience with parallel processing systems and compiler design

·       Background in MIS/database theory

·       Experience with process engineering and quality practices, including military, ISO, and other standards

·       Experience with a wide variety of computer platforms: SPARC (SunOS, Solaris), VAX (VMS, Unix), IBM 4381 (VM/CMS), PDP-11 (RMS, RT-11, Unix), DEC System-10/20 (TOPS), PCs (DOS, Windows, Linux), HP 700/1500/2000 (HP/UX), Wang VS, Apple II/III/Mac, Z-80 (CP/M), ARM (Nucleus, RTXC, Linux), 68k (VRTX/ARTX, pSOS), PowerPC (VxWorks, pSOS, Linux), home-built computers (1802, 6502, 8085, x86)

·       Experience with a vast assortment of programming languages and tools: C/C++, MATLAB, Quartus II, MAX PLUS, Java, C#, BASIC, Unix shells, Assemblers (DSP1600, DSP16000, ARM, 68k, x86, 8085, PDP-11, 6502, 1802, PowerPC, PIC, Gnu), SWIG, Python, Perl, Tcl/Tk, Incr Tcl, Awk, Lex, Yacc, Yacc++, Ada, Pascal, FORTRAN, APL, COBOL, Lisp, Prolog, Fit, make, nmake, Gnu make, PVM, Sablime, SCCS, CVS, RCS, MKS Source/Change/Track Integrity, CIA, Pi, HTML, Postscript, SQL, Unity, 20/20, dBase, SyBase, Oracle, troff, MS Office/Project/Visio/etc., Framemaker, and many others

·       Have been a member of various development teams for open-source projects including Python, SWIG, and Cygwin

PUBLICATIONS

·       “Developing a device driver for a System-on-a-Chip,” Software Symposium 2000

·       US Patent 5963742: Using Speculative Parsing To Process Complex Input Data

·       US Patent 5991539: Use of Re-Entrant Subparsing to Facilitate Processing of Complicated Input Data

·       US Patent 6314564: Method For Resolving Arbitrarily Complex Expressions At Link Time

·       Patents Pending: Condition Management System. Three patents pending

·       Patent Pending: Dynamic Multi-foveal Display Filter

·       Masters Thesis: Processor Support for Interval Arithmetic

EDUCATION

M.S. Computer Engineering. Lehigh University, Bethlehem, PA, May 1998. (GPA 3.99/4.0)

B.S. Computer Science. Stevens Institute of Technology, Hoboken, NJ, May 1988. (with Honors)

EXPERIENCE

·       Distinguished Member of Technical Staff. Agere Systems, Allentown, PA.
Fall 2003 – Present

System engineer for Agere IP Reuse group. Supported Monterey digital media player and Venango inkjet fax/copier ASICs in multiple roles from project conception through implementation and test. Provided requirements support for Tioga printer and imaging ASIC, TPM security IP block, and Ubiquitous HDD concept. Provided software API, hardware and software test platform, and back-end project management support for AES cryptography IP block. Developed system and other requirements as needed. Supported all aspects of software development on ARM 922T and 946 processors. Provided overall DSP support in multiple roles, including designing DSP test plans, debugging DSP tool issues, and designing DSP utility services and application architectures. Established software and hardware development and test platforms using Agere Wizard and Altera Excalibur (ARM/FPGA) development boards. Created an Altera EPXA10-based development platform for combined software and hardware validation. Rewrote Agere standard methodology bluebook for reusable software IP. Designed VOS operating system abstraction layer and ported it to Nucleus/Venango, RTXC/Monterey, and Excalibur platforms. Developed boot loaders for ARM 946 and Excalibur/922T processors. Designed, developed, and tested an image processing API and DSP scheduler. Incorporated relevant MISRA guidelines into methodology bluebook and software QIP standard quality evaluation form. Reformatted, evaluated, and entered reusable IP blocks into the Agere Systems IP Repository.

·       Distinguished Member of Technical Staff. Agere Systems, Murray Hill, NJ & Allentown, PA.
Fall 1998 – Fall 2003

System architect for Agere System-on-a-Chip offerings. Designed OS- and platform-independent drivers and on-chip software for devices with thousands of registers and complicated control requirements. Project lead for the development of drivers for several MARS-family devices, including an overhead processor, optical framer, and several framer/add-drop-mux devices, driving all aspects of development from initial requirements through final laboratory testing. Personal development duties included driver code, virtual test platforms (device cosimulators, fast register transactors), and bootstrapping of target platforms (MPC860, pSOS and VxWorks BSPs, networked test applications). Integrated Python and Tcl script engines. Wrote user documentation. Gave pre- and post-sales support to major customers. Performed laboratory validation for drivers and device verification for several blocks of a framer/add-drop-mux device. Specified requirements, designed, implemented, and tested virtual operating system layers and signal processing engines.

·       Member of Technical Staff. AT&T Bell Laboratories/Lucent Technologies, Allentown, PA.
Fall 1992 – Fall 1998

DSP tools developer. Developed tools for Lucent’s fixed-point DSP products, including assemblers, archivers, linkers, simulators (phase-accurate device models), code translators, and test suites for the DSP1600 and DSP16000 family. Helped design the DSP16000 ISA and specified new features for both families. Oversaw third-party support efforts, including C compiler and real-time operating system development. Developed signal processing, remote-host-support, and general-purpose DSP libraries. Developed a tiny DSP operating system. Reformed a failing software release process and coordinated the releases of multiple development groups. Served on a multi-lab software quality improvement team, leading the effort to define a standard software development process. Oversaw successful ISO 9001 certification efforts.

·       Member of Technical Staff - I. AT&T Bell Laboratories, Whippany, NJ.
Spring 1991 - Fall 1992

SLC-2000® Subscriber Loop Carrier project: Core designer of the SLC-2000 software development process, which included several innovative techniques later adopted by UML. Authored a unique requirements allocation process given particular attention by Watts Humphrey during an assessment for a Malcolm Baldridge award (the award was granted). Designed the communication system between the SLC-2000 and DDM-2000 Digital Data Multiplexer, the key component of the initial project release. Designed software to perform remote hardware testing via the Pair Gain Test Controller.

·       Member of Technical Staff - I. AT&T Bell Laboratories, Whippany, NJ.
Spring 1988 - Spring 1991

Enhanced Modular Signal Processor project: Developed software for a large real-time parallel signal processing system, including the software loader, communications modules for both RS-422 and proprietary interfaces, software to maintain and interpret the system configuration, and the system-wide built-in test and fault recovery system. Extensively tested local and system-wide fault recovery through physical fault insertion.

·          Canadian Imperial Bank of Commerce, New York, NY.
Summer 1987 - Spring 1988

Designed accounts reconciliation, syndication accounting, and letter of credit tracking systems on personal computers using Dataease and Paradox.

·       Stone & Webster Management Consultants, Inc., New York, NY.
Winter 1986 - Summer 1987

Ported a time and charges database from a DEC System/20 to personal computers using dBase. Adapted the database to the limited resources available and developed a new interface.

·       Ciba-Geigy Pharmaceutical Development, Project Management Department, Summit, NJ.
Summer 1986 - Winter 1986

Transferred the corporate project management system from a DEC System/20 to IBM 4381 and personal computers and developed queries and reports using Dataflex.

·       Ciba-Geigy Publications, Order Entry Department, West Caldwell, NJ.
Summer 1984

Created and maintained the order-entry system used to track all book sales.